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STWD100
Watchdog timer circuit
Features

Current consumption 13 A typ. Available watchdog timeout periods are 3.4 ms, 6.3 ms, 102 ms and 1.6 s Chip-enable input Open drain or push-pull WDO output Operating temperature range: -40 to +125 C Package SOT23-5, SC70-5 (SOT323-5) SOT23-5 (WY) SC70-5, SOT323-5 (W8)
July 2008
Rev 5
1/25
www.st.com 1
Contents
STWD100
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Watchdog output (WDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip-enable input (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1 Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 8
3 4 5 6 7 8 9
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STWD100
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. SOT23-5 and SC70-5 (SOT323-5) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SOT23-5 - 5-lead small outline transistor package mechanical data . . . . . . . . . . . . . . . . . 19 SC70 (SOT323-5) - 5-lead small outline transistor package mechanical data . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device versions with marking descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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List of figures
STWD100
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. SOT23-5 and SC70-5 (SOT323-5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Open drain WDO output connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Normal triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timeout without re-trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trigger after timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Enable pin, EN, triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SOT23-5 - 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 18 SC70 (SOT323-5) - 5-lead small outline transistor package outline. . . . . . . . . . . . . . . . . . 20
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STWD100
Description
1
Description
The STWD100 watchdog timer circuits are self-contained devices which prevent system failures that are caused by certain types of hardware errors (non-responding peripherals, bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.). The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). The input is used to clear the internal watchdog timer periodically within the specified timeout period, twd (see Section 3: Watchdog timing). While the system is operating correctly, it periodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is not reset, a system alert is generated and the watchdog output, WDO, is asserted (see Section 3: Watchdog timing). The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable or disable the watchdog functionality. The EN pin is connected to the internal pull-down resistor. The device is enabled if the EN pin is left floating. Figure 1. SOT23-5 and SC70-5 (SOT323-5) package connections
WDO GND EN
1 2 3
5
VCC WDI
AI12639b
4
Table 1.
SOT23-5 and SC70-5 (SOT323-5) pin description
Pin number 1 2 3 4 5 Name WDO GND EN WDI VCC Description Watchdog output Ground Enable pin Watchdog Input Supply voltage
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Description
STWD100
Figure 2.
Logic diagram
VCC
WDI STWD100 EN WDO
GND
AI12640a
Note:
WDO output is available in open drain or push-pull configuration. Figure 3. Block diagram
WDI
WDI Transitional Detector Watchdog Timer (STWD100xP only)
Output Timing CLR
WDO
EN
GND
AI12641b
Note:
Positive pulse on enable pin EN longer than 1 s resets the watchdog timer.
6/25
STWD100
Operation
2
Operation
The STWD100 device is used to detect an out-of-control MCU. The user has to ensure watchdog reset within the watchdog timeout period, otherwise the watchdog output is asserted and MCU is restarted. The STWD100 can be also enabled or disabled by the chipenable pin.
2.1
Watchdog input (WDI)
The WDI input has to be toggled within the watchdog timeout period, tWD, otherwise the watchdog output, WDO, is asserted. The internal watchdog timer, which counts the tWD period, is cleared either: 1. 2. 3. by a transition on watchdog output, WDO (see Figure 8) or by a pulse on enable pin, EN (see Figure 10) or by toggling WDI input (low-to-high on all versions and high-to-low on STWD100xW, STWD100xX and STWD100xY only).
The pulses on WDI input with a duration of at least 1 s are detected and glitches shorter than 100 ns are ignored. If WDI is permanently tied high or low and EN is tied low, the WDO toggles every 3.4 ms (tWD) on STWD100xP and every tWD and tPW on STWD100xW, STWD100xX and STWD100xY (see Figure 8).
2.2
Watchdog output (WDO)
When the VCC exceeds the timer startup voltage VSTART after power-up, the internal watchdog timer starts counting. If the timer is not cleared within the tWD, the WDO will go low (see Figure 6). After exceeding the tWD, the WDO is asserted for tPW on STWD100xW, STWD100xX and STWD100xY regardless of possible WDI transitions (see Figure 9). On STWD100xP WDO is asserted for a minimum of 10 s and a maximum of tWD after exceeding the tWD period (see Figure 8 and Figure 9). The STWD100 has an active-low open drain or push-pull output. An external pull-up resistor connected to any supply voltage up to 6 V is required in case of open drain WDO output (see Figure 4). Select a resistor value large enough to register a logic low, and small enough to register a logic high while supplying all input current and leakage paths connected to the reset output line. A 10 k pull-up resistor is sufficient in most applications.
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Operation Figure 4. Open drain WDO output connection
STWD100
STWD100
+3.3 V 10 k VCC WDI WDO EN GND
5 V System
+5.0 V
GND
AI12645a
2.3
Chip-enable input (EN)
All states mentioned in Section 2.1: Watchdog input (WDI) and Section 2.2: Watchdog output (WDO) are valid under the condition that EN is in logical low state. The behavior of EN is common to all versions (i.e. STWD100xP, STWD100xW, STWD100xX and STWD100xY). If the EN goes high after power-up in less than tWD from the moment that VCC exceeds the timer startup voltage, VSTART, the WDO will stay high for the same time period as EN, plus tWD (see Figure 10). If the EN goes high anytime during normal operation, the WDO will go high as well, but the minimum possible WDO pulse width is 10 s (see Figure 10). The pulses on the EN pin with a duration of at least 1 s are detected and glitches shorter than 100 ns are ignored.
2.4
2.4.1
Applications information
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STWD100 watchdog output, WDO. For example, if the WDO output is driven high and the micro wants to pull it low, signal contention will result. To prevent this from occurring, connect a 4.7 k resistor between the WDO output and the micro's reset I/O as in Figure 5.
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STWD100 Figure 5. Interfacing to microprocessors with bidirectional reset I/O
Buffered Reset to other System Components
Operation
VCC
VCC 4.7 k
STWD100
WDO
Microprocessor
RST
GND
GND
AI12643a
9/25
Watchdog timing
STWD100
3
Figure 6.
Watchdog timing
Power-up
Power up: Watchdog timer starts running as soon as VCC rises above ~ 2.2 V. ~ 2.2 V VCC At power up, WDI is a don't care. It can be 1 or 0. Can also transition from high to low. WDI Low-to-high transition on WDI will reset timer. But no input transition is required to begin timing. WDO EN X X (ie, 1 or 0 but not floating) tWD
STWD100xP
STWD100xW, STWD100xX, STWD100xY
Power up: Watchdog timer starts running as soon as VCC rises above ~ 2.2 V. ~ 2.2 V VCC
At power up, WDI is a don't care. It can be 1 or 0. Low-to-high or high-to-low transition on WDI will reset timer. But no input transition is required to begin timing. WDI X (ie, 1 or 0 but not floating) tWD
WDO EN X
AI12662
10/25
STWD100
Watchdog timing
Figure 7.
Normal triggering
STWD100xP
VCC Trigger only on rising edge. Falling edge is ignored.
WDI tWD
WDO EN X
STWD100xW, STWD100xX, STWD100xY
VCC Trigger on rising and falling edge of WDI. WDI < tWD WDO EN X
AI12663
tWD
11/25
Watchdog timing
STWD100
Figure 8.
Timeout without re-trigger
STWD100xP
After a timeout and WDO is asserted, it will stay low for tWD time period, then return high. If no WDI trigger event occurs, WDO will again assert low after tWD time period. This cycle repeats until a WDI trigger event occurs. VCC
WDI tWD WDO EN X tWD tWD tWD tWD tWD
STWD100xW, STWD100xX, STWD100xY
After a timeout and WDO is asserted, it will stay low for tPW time period, then return high. If no WDI trigger event occurs within tWD time period, WDO will again assert low. This cycle repeats until a WDI trigger event occurs while WDO is high.
VCC
WDI tWD WDO EN X
AI12664
tPW
tWD
tPW
tWD
tPW
tWD
12/25
STWD100
Watchdog timing
Figure 9.
Trigger after timeout
STWD100xP
VCC If a WDI trigger occurs after the WDO output has asserted, the output will de-assert, but with a pulse width of at least 10 s (min).
WDI t WD WDO EN X >10 s min.
STWD100xW, STWD100xX, STWD100xY
If a WDI trigger occurs after the WDO output has asserted, it is ignored, and the output remains asserted for the specified time, tPW.
VCC Trigger ignored while WDO is low. WDI t PW WDO EN X
AI12665
13/25
Watchdog timing
STWD100
Figure 10. Enable pin, EN, triggering
STWD100xx
~ 2.2 V Whenever EN is high, all timing is reset, and the part is disabled. Timing commences from 0 when EN goes low. VCC
WDI WDO
X (ie, 1 or 0 but not floating)
< tWD EN X DISABLED
tWD
STWD100xx
VCC If EN goes high while WDO is asserted, WDO will de-assert but only after the nominal minimum pulse width of 10 s has elapsed.
WDI
X (ie, 1 or 0 but not floating) tWD
WDO tWD >10 s min. EN X DISABLED
AI12666
14/25
STWD100
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in Table 2 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2.
Symbol TSTG TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation Value -55 to 150 260 -0.3 to VCC +0.3 -0.3 to 7.0 20 320 Unit C C V V mA mW
1. Reflow at peak temperature of 260 C (total thermal budget not to exceed 245 C for greater than 30 seconds).
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DC and AC parameters
STWD100
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 3. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3. Operating and AC measurement conditions
Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Value 2.7 to 5.5 -40 to 125 5 0.2 to 0.8 VCC 0.3 to 0.7 VCC Unit V C ns V V
16/25
STWD100 Table 4.
Sym VCC ICC ILO
DC and AC parameters DC and AC characteristics
Description Test condition(1) Min 2.7 Typ 5 13 from output to the GND or VCC -1 -1 0.7 VCC 0.3 VCC VCC 2.7 V, ISINK = 1.2 mA VCC 4.5 V, ISINK = 3.2 mA 0.8 VCC 0.8 VCC 0.3 0.4 Max 5.5 26 +1 +1 Unit V A A A V V V V V V
Operating voltage VCC supply current Open drain output leakage current Input leakage current (WDI)
VIH VIL VOL
Input high voltage (WDI, EN) Input low voltage (WDI, EN) Output low voltage (WDO)
VOH
Output high voltage (WDO) (push-pull VCC 2.7 V, ISOURCE = 500 A only) VCC 4.5 V, ISOURCE = 800 A
Enable pin ( EN) EN input pulse width EN glitch rejection EN-to-WDO delay(2) 32 1 100 200 63 100 s ns ns k
EN pull-down resistance Watchdog Timer VSTART Timer startup voltage STWD100xP STWD100xW tWD Watchdog timeout period STWD100xX STWD100xY tPW Watchdog active time WDI-to-WDO delay(3)
1.9 2.3 4.3 71 1.12 140
2.2 3.4 6.3 102 1.6 210 150
2.7 4.6 8.6 142 2.24 280
V ms ms ms s ms ns s
WDI pulse width WDI glitch rejection
1 100
ns
1. Valid for ambient operating temperature: TA = -40 to 125 C; VCC = 2.7 V to 5.5 V except where noted. 2. WDO will assert for minimum of 10 s even if EN transitions high. 3. WDO will assert for minimum of 10 s regardless of transition on WDI (valid for STWD100xP only).
17/25
Package mechanical data
STWD100
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 11. SOT23-5 - 5-lead small outline transistor package mechanical drawing
SOT23-5
18/25
STWD100 Table 5.
Symbol Typ A A1 A2 B C D D1 E e F K L 0.35 1.05 0.40 0.15 2.90 1.90 2.80 0.95 1.60 1.50 0 0.10 1.75 10 0.60 0.014 2.60 3.00 0.90 0.35 0.09 2.80 1.20 Min 0.90 Max 1.45 0.15 1.30 0.50 0.20 3.00 0.041 0.016 0.006 0.114 0.075 0.110 0.037 0.063 Typ 0.047
Package mechanical data SOT23-5 - 5-lead small outline transistor package mechanical data
millimeters inches Min 0.035 Max 0.057 0.006 0.035 0.014 0.004 0.110 0.051 0.020 0.008 0.118
0.102
0.118
0.059 0 0.004
0.069 10 0.024
19/25
Package mechanical data
STWD100
Figure 12. SC70 (SOT323-5) - 5-lead small outline transistor package outline
SC70(SOT323-5)
20/25
STWD100
Package mechanical data
Table 6.
SC70 (SOT323-5) - 5-lead small outline transistor package mechanical data
mm inches Max 1.10 0.10 1.00 0.30 0.22 2.20 2.40 1.35 0.079 0.083 0.049 0.026 0.051 0.26 0 5 0.46 8 0.014 - 0.010 0 5 0.018 8 0.035 Typ Min 0.031 0.000 0.031 0.006 0.004 0.071 0.071 0.045 Max 0.043 0.004 0.039 0.012 0.009 0.087 0.094 0.053
Symbol Typ A A1 A2 b c D E E1 e e1 L < N 2.00 2.10 1.25 0.65 1.30 0.36 - 0.90 Min 0.80 0.00 0.80 0.15 0.10 1.80 1.80 1.15
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Part numbering
STWD100
7
Table 7.
Example:
Part numbering
Ordering information scheme
STWD100 N P WY 3 F
Device type STWD100
Output type N: Open drain (active low) P: Push-pull (active low)
Device version P: tWD = 3.4 ms, tPW = tWD = 3.4 ms W: tWD = 6.3 ms, tPW = 210 ms X: tWD = 102 ms, tPW = 210 ms Y: tWD = 1.6 s, tPW = 210 ms
Package WY: SOT23-5 W8: SC70-5 (SOT323-5)
Temperature range 3: -40 to +125 C
Shipping method E: ECOPACK(R) package, tubes F: ECOPACK(R) package, tape & reel
Note:
Contact local ST sales office for availability of device versions other than STWD100NPWY3F.
22/25
STWD100
Package marking information
8
Table 8.
Package marking information
Device versions with marking descriptions
(1)
Part number
Watchdog timing period twd tpw 3.4 ms 210 ms 210 ms 210 ms 210 ms 210 ms 210 ms
Output configuration
Topside marking
Bottomside marking(2) PYWW PYWW PYWW PYWW PYWW PYWW PYWW
STWD100NPxxxx STWD100NWxxxx STWD100NXxxxx STWD100NYxxxx STWD100PWxxxx STWD100PXxxxx STWD100PYxxxx
3.4 ms 6.3 ms 102 ms 1.6 s 6.3 ms 102 ms 1.6 s
open drain open drain open drain open drain push-pull push-pull push-pull
WNP WNW WNX WNY WPW WPX WPY
1. Contact local ST sales office for availability of device versions other than STWD100NPWY3F. 2. Description: P = assembly plant code, Y = assembly year (0 to 9), WW = assembly work week ((01 to 52).
23/25
Revision history
STWD100
9
Revision history
Table 9.
Date 08-Nov-2007 23-Jan-2008 28-Jan-2008 17-Mar-2008 31-Jul-2008
Document revision history
Revision 1 2 3 4 5 Initial release. Updated cover page and Table 4; document status upgraded to full datasheet. Updated cover page. Updated cover page, Figure 4, 7, 9, and Table 4, 8. Updated Features on cover page and Table 4. Changes
24/25
STWD100
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